PIN CONFIGURATION OF 8085

Pin Configuration of 8085 Microprocessors

Address Bus (A6 - A15 )

The most significant 8 bits of the memory address or the 8 bits of the I/0

address,3 stated during Hold and Halt modes.

Mulitiplexed Address/DataBus (AD0 - AD7 )

Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 address)

appear on the bus during the first clock cycle of a machine state. It then becomes the

data bus during the second and third clock cycles. 3 stated during Hold and Halt

modes.

ALE (Output)

Address Latch Enable: It occurs during the first clock cycle of a machine state and

enables the address to get latched into the on chip latch of peripherals. The falling

edge of ALE is set to guarantee setup and hold times for the address information.

ALE can also be used to strobe the status information. ALE is never 3stated.

SO, S1 (Output)

S1 S0

O O HALT

0 1 WRITE

1 0 READ

1 1 FETCH

S1 can be used as an advanced R/W status.

RD

READ; indicates the selected memory or 1/0 device is to be read and that the Data

Bus is available for the data transfer.

WR

WRITE; indicates the data on the Data Bus is to be written into the selected memory

or 1/0 location. Data is set up at the trailing edge of WR. 3stated during Hold and Halt

modes.

READY (Input)

If Ready is high during a read or write cycle, it indicates that the memory or

peripheral is ready to send or receive data. If Ready is low, the CPU will wait for

Ready to go high before completing the read or write cycle.

HOLD (Input)

HOLD; indicates that another Master is requesting the use of the Address and Data

Buses. The CPU, upon receiving the Hold request. will relinquish the use of buses as

soon as the completion of the current machine cycle. Internal processing can continue.

The processor can regain the buses only after the Hold is removed. When the Hold is

acknowledged, the Address, Data, RD, WR, and IO/M lines are 3stated.

HLDA

HOLD ACKNOWLEDGE; indicates that the CPU has received the Hold request and

that it will relinquish the buses in the next clock cycle. HLDA goes low after the Hold

request is removed. The CPU takes the buses one half clock cycle after HLDA goes

low.

INTR (Input)

INTERRUPT REQUEST; is used as a general purpose interrupt. It is sampled only

during the next to the last clock cycle of the instruction. If it is active, the Program

Counter (PC) will be inhibited from incrementing and an INTA will be issued. During

this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt

service routine. The INTR is enabled and disabled by software. It is disabled by Reset

and immediately after an interrupt is accepted.

INTA (Output)

INTERRUPT ACKNOWLEDGE; is used instead of (and has the same timing as) RD

during the Instruction cycle after an INTR is accepted. It can be used to activate the

8259 Interrupt chip or some other interrupt port.

RST 5.5

RST 6.5 - (Inputs)

RST 7.5

RESTART INTERRUPTS; These three inputs have the same timing as I NTR except

they cause an internal RESTART to be automatically inserted.

RST 7.5 ~~ Highest Priority

RST 6.5

RST 5.5 o Lowest Priority

The priority of these interrupts is ordered as shown above. These interrupts have a

higher priority than the INTR.

TRAP (Input)

Trap interrupt is a nonmaskable restart interrupt. It is recognized at the same time as

INTR. It is unaffected by any mask or Interrupt Enable. It has the highest priority of

any interrupt.

RESET IN (Input)

Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA

flipflops. None of the other flags or registers (except the instruction register) are

affected The CPU is held in the reset condition as long as Reset is applied.

RESET OUT (Output)

Indicates CPlJ is being reset. Can be used as a system RESET. The signal is

synchronized to the processor clock.

X1, X2 (Input)

Crystal or R/C network connections to set the internal clock generator X1 can also be

an external clock input instead of a crystal. The input frequency is divided by 2 to

give the internal operating frequency.

CLK (Output)

Clock Output for use as a system clock when a crystal or R/ C network is used as an

input to the CPU. The period of CLK is twice the X1, X2 input period.

IO/M (Output)

IO/M indicates whether the Read/Write is to memory or l/O Tristated during Hold and

Halt modes.

SID (Input)

Serial input data line The data on this line is loaded into accumulator bit 7 whenever a

RIM instruction is executed.

SOD (output)

Serial output data line. The output SOD is set or reset as specified by the SIM

instruction.

Vcc

+5 volt supply.

Vss

Ground Reference.

Flags

The ALU includes five flip-flops, which are set or reset after an operation according

to data conditions of the result in the accumulator and other registers.

They are called

Zero(Z)

Carry (CY)

Sign (S)

Parity (P)

Auxiliary Carry (AC)

The most commonly used flags are Zero, Carry, and Sign. The microprocessor uses these flags to test data conditions.

For example, after an addition of two numbers, if the sum in the accumulator id larger than eight bits, the flip-flop uses to indicate a carry is called the Carry flag (CY) which is

set to one. When an arithmetic operation results in zero, the flip-flop called the

Zero(Z) flag is set to one.

Program Counter (PC)

This 16-bit register deals with sequencing the execution of instructions. This register

is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a

16-bit register.

The microprocessor uses this register to sequence the execution of the instructions.

The function of the program counter is to point to the memory address from which the

next byte is to be fetched. When a byte (machine code) is being fetched, the program

counter is incremented by one to point to the next memory location

Stack Pointer (SP)

The stack pointer is also a 16-bit register used as a memory pointer. It points to a

memory location in R/W memory, called the stack. The beginning of the stack is

defined by loading 16-bit address in the stack pointer. The stack concept is explained

in the chapter "Stack and Subroutines."

Instruction Register/Decoder

Temporary store for the current instruction of a program. Latest instruction sent here

from memory prior to execution. Decoder then takes instruction and ‘decodes’ or

interprets the instruction. Decoded instruction then passed to next stage.

Memory Address Register

Holds address, received from PC, of next program instruction. Feeds the address bus

with addresses of location of the program under execution.

Control Generator

Generates signals within uP to carry out the instruction which has been decoded. In

reality causes certain connections between blocks of the uP to be opened or closed, so

that data goes where it is required, and so that ALU operations occur.

Register Selector

This block controls the use of the register stack in the example. Just a logic circuit

which switches between different registers in the set will receive instructions from

8085 Architecture

Arithmetic Logic Unit

The ALU performs the actual numerical and logic operation such as ‘add’, ‘subtract’,
‘AND’, ‘OR’, etc. Uses data from memory and from Accumulator to perform
arithmetic. Always stores result of operation in Accumulator.

Control Unit

Generates signals within uP to carry out the instruction, which has been decoded. In
reality causes certain connections between blocks of the uP to be opened or closed, so
that data goes where it is required, and so that ALU operations occur.


Registers
The 8085/8080A-programming model includes six registers, one accumulator, and
one flag register, as shown in Figure. In addition, it has two 16-bit registers: the

stackpointer and the program counter.

They are described briefly as follows.
The 8085/8080A has six general-purpose registers to store 8-bit data; these are
identified as B,C,D,E,H, and L as shown in the figure. They can be combined as
register pairs - BC, DE, and HL - to perform some 16-bit operations. The
programmer can use these registers to store or copy data into the registers by using
data copy instructions.

Accumulator

The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This register is used to store 8-bit data and to perform arithmetic and logical operations.The result of an operation is stored in the accumulator. The accumulator is also identified as register A.